It is becoming increasingly common for metal oxide semiconductor (“MOS”) transistors to be produced utilizing semiconductor-on-insulator (SOI) substrates. A conventional SOI substrate includes a thin layer of silicon overlaying an intermediate insulating layer, which is supported by a carrier wafer. The intermediate insulating layer typically comprises silicon oxide and is commonly referred to as a “buried oxide” or “BOX” layer. In certain instances, the silicon layer overlaying the BOX layer may be scaled down in proportion to the dimensions of other device parameters (e.g., gate length). When the overlaying silicon layer has a thickness less than a minimum threshold (e.g., approximately 20 nm), the SOI substrate is commonly referred to as an “ultra thin body” SOI or, more simply, a “UTB” SOI substrate. UTB body thickness is substantially equal to the depletion zone of the transistor and is commonly referred to as a “fully depleted”. Relative to partially depleted SOI devices, fully depleted UTB SOI minimizes floating body effects and, thus, permits the switching behavior of the transistor to be substantially unaffected by the transistor's previous state.
Relative to MOS transistors produced on bulk wafers, MOS transistors produced on UTB SOI substrates generally achieve lower junction capacitances and higher operational speeds. However, MOS transistor produced on UTB SOI substrates, tend to exhibit high series resistance. It has recently been proposed that full silicidation of the source/drain (“S/D”) regions within a UTB SOI substrate could be performed to form Schottky-like junctions and thereby reduce the series resistance of the transistors ultimately formed on the substrate. However, conventional silicidation processes, including state-of-the-art nickel silicidation processes, have proven less than ideal for this purpose. Due to inherent variations in local silicon film thickness from transistor to transistor, it can be excessively difficult to determine the appropriate volume of silicide-forming material (e.g., nickel) to deposit over a particular transistor formed on a UTB SOI substrate. If too little silicide-forming material is deposited, full silicidation of the S/D regions will not be achieved. Conversely, if too great a volume of silicide-forming material is deposited, the excess silicide-forming material tends to migrate laterally into the channel region and react within the silicon of the channel in a poorly controlled manner. Reaction of the excess silicide-forming material with the silicon of the channel results in the formation of a highly erratic (e.g., jagged) S/D-channel interface. On an individual device level, the formation of a highly erratic S/D-channel interface can cause significant current variations and increased likelihood of channel shorts. On a manufacturing level, the formation of high erratic S/D-channel interfaces reduces device throughput and increases overall cost of production.
Considering the above, it is desirable to provide a method for fabricating a semiconductor device utilizing a thin body substrate, such as a fully depleted ultra-thin body silicon-on-insulator substrate, wherein full silicidation of the S/D regions is achieved in a highly controllable manner to increase product conformity and throughput while reducing the overall cost of manufacture. Preferably, embodiments of such a method would be suitable for use in the production of both planar semiconductor devices and non-planar semiconductor devices, such as FinFETs and trigates. Other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.